ECTS
3 credits
Training Structure
College of Sciences
Description
- Controller overview.
- Robust synthesis and risk management.
- Representation and synthesis of synchronous machines.
- Description/synthesis language.
- The basics of the VHDL language (entities, architecture, etc.).
- Behavioral and structural descriptions.
- Simulation (Testbench).
- Reprogrammable circuits (SPLDs, CPLDs, FPGAs).
Objectives
- Master the use of state diagrams to represent a system.
- Create a state graph (incorporating the concepts of robustness and risk management)
- Enable students to use a high-level description language (VHDL) to describe a circuit or system.
- Master the programming workflow for programmable circuits (using Xilinx's Vivado tool).
Class Hours
- Logic Synthesis / VHDL - LabLab15 hours
- Logic Synthesis / VHDL - LectureLecture12 hours
Mandatory Prerequisites
Combinational and sequential logic.
Additional Information
CM: 12:00 p.m.
Practical Training: 3:00 p.m.