Logic Synthesis / VHDL

- Controller Summary.

- Robust synthesis and contingency management.

- Representation and synthesis of synchronous machines.

- Description/synthesis language.

- The basics of the VHDL language (entity, architecture, ...).

- Behavioral and structural descriptions.

- Simulation (Testbench).

- Reprogrammable circuits (SPLD, CPLD, FPGA).

- Master the state graph representation of a system.

- Synthesize a state graph (with the notion of robustness and hazard management)

- Enable the student to use a high-level description language (VHDL) to describe a circuit/system.

- Master the programming flow of programmable circuits (using Xilinx's Vivado tool).

Combinatorial and sequential logic.

CM: 12h

Practical work: 15h