Logic synthesis / VHDL

- Controller synthesis.

- Robust synthesis and hazard management.

- Representation and synthesis of synchronous machines.

- Description/synthesis language.

- The basics of the VHDL language (entity, architecture, ...).

- Behavioral and structural descriptions.

- Simulation (Testbench).

- Reprogrammable circuits (SPLD, CPLD, FPGA).

- Master the state graph representation of a system.

- Synthesize a state graph (with the notion of robustness and hazard management)

- To enable the student to use a high-level description language (VHDL) to describe a circuit/system.

- Master the programming flow of programmable circuits (Use of the Vivado tool from Xilinx).

Combinatorial and sequential logic.

CM : 12h

TP : 15h