Logic Synthesis / VHDL

- Controller summary.

- Robust synthesis and risk management.

- Representation and synthesis of synchronous machines.

- Description/synthesis language.

- The basics of the VHDL language (entity, architecture, etc.).

- Behavioral and structural descriptions.

- Simulation (Testbench).

- Reprogrammable circuits (CPLD, FPGA).

- Master the state graph representation of a system.

- Synthesize a state graph (with the concept of robustness and risk management)

- Enable students to use a high-level description language (VHDL) to describe a circuit/system.

- Mastering the programming flow of programmable circuits (using Xilinx's Vivado tool).

Combinatorial and sequential logic.

CM: 12 p.m.

Practical work: 3 p.m.