ECTS
3 credits
Component
Faculty of Science
Description
- Controller Summary.
- Robust synthesis and contingency management.
- Representation and synthesis of synchronous machines.
- Description/synthesis language.
- The basics of the VHDL language (entity, architecture, ...).
- Behavioral and structural descriptions.
- Simulation (Testbench).
- Reprogrammable circuits (CPLD, FPGA).
Objectives
- Master the state graph representation of a system.
- Synthesize a state graph (with the notion of robustness and hazard management)
- Enable the student to use a high-level description language (VHDL) to describe a circuit/system.
- Master the programming flow of programmable circuits (using Xilinx's Vivado tool).
Necessary prerequisites
Combinatorial and sequential logic.
Further information
CM: 12h
Practical work: 15h